1. Field of the Invention
This invention relates to computer hardware and, more particularly, to virtual memory mechanisms including address translation mechanisms.
2. Description of the Related Art
Many modern computer systems may include a fixed amount of physical system memory that may serve as a repository for applications and data during computer system operation. Often, physical system memory (or simply physical memory) consists of some form of random access memory (RAM) such as dual data rate synchronous dynamic RAM (DDR-SDRAM), for example. Operating system software may manage how applications and data are organized within physical memory, and system devices such as microprocessors and input/output (I/O) devices may access and modify physical memory contents through mechanisms such as load and store instructions and direct memory access (DMA) transactions, respectively.
Allowing application software to directly access physical memory may present security and stability concerns. For example, a rogue application program may violate system security by attempting to access confidential data residing in physical memory, such as passwords or security codes, for example. Similarly, a runaway program may inadvertently overwrite system data structures and code critical for system operation, such as operating system kernel code and task scheduling tables, resulting in unstable operation or a system crash. Further, providing a fixed amount of physical memory in a system may limit the number and size of applications that can be active at any given time.
To help address these concerns, many computer systems may provide support for a virtual memory mechanism. In one embodiment, such a mechanism may include providing support for a virtual memory address space distinct from the physical memory address space and providing application programs and data access only to the virtual address space. A mapping or translation, referred to herein as a physical address translation, may then be created between a given virtual memory address and a physical memory address by operating system software and/or computer hardware, such as a microprocessor. Virtual memory support may enable computer systems to segregate application code segments from each other and from sensitive data by providing a means of controlling access to privileged physical memory translations.
Virtual memory support may also provide a mechanism to augment the virtual address space available for application programs and data without necessarily increasing the amount of physical memory included in the system. For example, inactive application code may be relocated from physical memory to a slower storage medium such as a hard drive without deallocating the virtual address space occupied by the inactive application code, a process that may be referred to as swapping. The physical address translation for a virtual address may indicate whether the relevant memory contents have been swapped to hard drive storage, so that operating system software may transfer them back to physical memory if a request to the swapped virtual address is made.
In some embodiments, translation of a virtual address to a physical address may be accomplished through multiple levels of indirection, such as by referencing a hierarchy of memory page translation tables defined by operating system software and/or microprocessor support. Such a hierarchical structure may provide flexibility in how a given virtual address may be mapped to a physical address, but traversing such a structure each time a memory access is attempted may be time-consuming. Therefore, in some embodiments, frequently used physical address translations may be cached within a microprocessor structure referred to as a translation lookaside buffer (TLB). In some embodiments, translations may be processed separately for instruction memory accesses and data memory accesses. For example, a microprocessor may include a TLB dedicated to caching instruction fetch-related physical memory translations. Such a TLB may be referred to herein as an instruction TLB (ITLB).
A larger ITLB may be able to cache more physical address translations, which may result in improved performance as the number of hierarchical translation table references during the course of instruction fetching is reduced. However, as an ITLB increases in size, its power consumption and access latency may increase accordingly. Increased power consumption in microprocessors may result in more expensive system costs, such as more sophisticated thermal management solutions to remove additional waste heat as well as more robust power supplies to supply the increased system power demands. Therefore, the increased power consumption associated with ITLB accesses may contribute to increased system costs due to overall microprocessor power consumption.